Tag Archives: Verilog
Open-source FPGA Stereo Vision Core released
The first version of my open-source OpenCV–compatible FPGA Stereo Correspondence Core is now available! (have a look at my previous FPGA Stereo Vision Project post for some more context) It’s written purely in synthesizable Verilog, and uses device-agnostic inference for … Continue reading
FPGA Stereo Vision Project
As alluded to in a few of my other posts, I’m working on developing an open-source FPGA-accelerated vision platform. This post is a detailed overview of the project’s architecture and general development methodology. Future (and past) posts will elaborate on … Continue reading
Inferring true dual-port, dual-clock RAMs in Xilinx and Altera FPGAs
Yes, it’s actually possible! – in Verilog and VHDL, even. I’m a big fan of inference, especially as it applies to writing synthesizable Verilog code for FPGAs. Properly coded, a module that infers technology-dependent blocks (e.g. block RAMs) should: be … Continue reading
danstrother.com 